In-memory computing (IMC) has emerged as an attractive complement to digital accelerators for enhancing the energy efficiency of machine learning tasks. IMC addresses the energy and latency costs of memory accesses dominating AI workloads by transforming the conventional memory accesses into one that computes functions of data in the memory core in an analog/mixed-signal manner. As a result, IMC chips have demonstrated > 100X reduction in the energy-delay product over equivalent von Neumann architectures at iso-accuracy. IMCs also exhibit a fundamental energy vs. SNR trade-off that designers need to exploit to enhance energy efficiency while meeting task-level accuracy requirements. Since the publication of the concept in our ICASSP 2014 paper,  IMC design has become an active area of research in the machine learning integrated circuits and architecture communities. This talk will describe IMC design principles, review current trends based on our recent efforts in extensive benchmarking (https://github.com/naresh-shanbhag/UIUC-IMC-Benchmarking), and identify future opportunities and challenges in deploying IMCs at scale in emerging applications.

Note that the seminar takes place on Tuesday, 14th March.

Presential in the IFISC seminar room

Zoom stream at: https://zoom.us/j/98286706234?pwd=bm1JUFVYcTJkaVl1VU55L0FiWDRIUT09